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dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 1 modern power electronics pr oducts require small size a nd lighter weight of power electronics parts. filter induc tor and capacitor sizes must be small. with the small filter, the switching semiconductor devices must have small switching loss. and heat sink also must be reduced. for the safe operation with the small heat sink, the switching semiconductor devices must have small condu ction loss. ixys developed new generation of trench mosfet (trench2 tm ), which has small gate ch arge and low on-resistance. the mosfet will be well suited for high power applications of synchronous dc to dc converters used in various systems. the mosfet is rugged and has avalanche energy capability. table 1: few examples of ixys trencht2 tm n-channel power mosfets part number vdss (max) (v) id @ tc=25c (a) rds(on) @ tj=25c ( ? ) ciss (pf) qg (nc ) trr @ tj= 25c (ns) r(th)jc (c/w) pd (w) e as (mj) package type ixta220n04t2 ? 40 220 0.0035 6500 112 45 0.42 360 ? 600 ? to \ 263 ? ixtp220n04t2 ? 40 220 0.0035 6500 112 45 0.42 360 ? 600 ? to \ 220 ? ixta90n055t2 ? 55 90 0.0084 2670 42 37 1.0 150 ? 300 ? to \ 263 ? ixtp90n055t2 55 90 0.0084 2670 42 37 1.0 150 ? 300 ? to \ 220 ? ixta110n055t2 55 110 0.0066 3060 57 38 0.82 180 ? 400 ? to \ 263 ? ixtp110n055t2 55 110 0.0066 3060 57 38 0.82 180 ? 400 ? to \ 220 ? ixta200n055t2 55 200 0.0042 6800 109 49 0.42 360 ? 600 ? to \ 263 ? ixtp200n055t2 55 200 0.0042 6800 109 49 0.42 360 ? 600 ? to \ 220 ? ixta70n075t2 75 70 0.012 2580 46 48 1.0 150 ? 300 ? to \ 263 ? IXTP70N075T2 75 70 0.012 2580 46 48 1.0 150 ? 300 ? to \ 220 ? ixta90n075t2 75 90 0.010 3100 54 50 0.82 180 ? 400 ? to \ 263 ? ixtp90n075t2 75 90 0.010 3100 54 50 0.82 180 ? 400 ? to \ 220 ? dc-to-dc synchronous converter design: figure 1: s ynchronous buck converter using ixys trencht2 tm power mosfet
dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 2 in figure 1, the q1 is called the high-si de or control fet and q2 is called the low-side or sync fet applied in a st ep-down dc to dc synchronous converter application. the ratio vin vo / is controlled by the duty cycle of q1. to improve the efficiency, it?s desirable to have q2 turn ed on when q1 is turned off. a simplified switch state diagram is shown in figure 2 [2 ]. it depicts the switching sequence as a-b- c-b-a where the state b called ?dead tim e? when both q1 and q2 are off and the schottky diode, d1 is on to provide the free wheeling operation in the inductive load circuit. it?s desirable to reduce the dead ti me to a minimum to improve the efficiency. however, if the dead time is lower than the turn-on or turn-off times of q1 and q2, the circuit may go into state d, the shoot-through state when both q1 and q2 are on at the same time causing a short-circuit in the i nput voltage source, vi n. the state d is undesirable since it would dest roy transistors q1 and q2. figure 2: circuit switc h state diagram [2]
dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 3 figure 3: ideal circuit waveforms (with no dead time) the switching period, off on s t t t + = , the switching frequency, s s t f 1 = the duty cycle, off on on s on t t t t t d + = = , turn-on time, s on dt t = turn-off time, s off t d t ) 1 ( ? = . figure 4: ideal synchronous buck converter inductor current an output dc voltage with lowe st ripple is considered the best solution. ripple appears in the output voltage as the l1 current? s ripple component, ) ( 1 t i l , which charges and discharges the output capacitor, c1, as s hown in figure 4. c1 is charged during the
dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 4 period when ) ( 1 t i l is greater than i o . the charge ( q ) that flows into c1 at this time divided by the value of c1 is th e output voltage ripple component. output inductor ripple current and voltage: the inductor voltage can be defined as, vo vin dt di l v l ? = = 1 , or, 1 ) ( ) ( 1 l vo vin t t i i l ? = = , here, dts ton t = = the inductor ripp le current is, ) ( 1 t i l = 1 ) ( 1 l f vo vin d l vo vin dts s ? ? = ? (1) the charge, q , indicated in figure 5, can be dete rmined by calculating the area of the triangle with height 2 ) ( 1 t i l and width 2 ts shown in figure 5. s l s l s l f t i t t i t t i q 8 ) ( 8 ) ( 2 2 ) ( 2 1 1 1 1 = ? = ? ? = the ripple voltage is, ) ( ) ( 2 ) 1 ( 1 1 8 ) 1 ( 1 8 ) ( 1 ) ( 2 2 2 1 t v f f vo d c l vints d d c ts t i c q t v o s c l l = ? = ? = = = (2) where, 1 1 2 1 c l f c = , output low pass filter (lpf) resonant frequency, = s f the switching frequency. the inductor value of l1 and the effective seri es resistance (esr) of the output capacitor, c1, a ffect the output ripple voltage, l v . a capacitor with the lowest possible esr is recommended for the application. for example, 4.7?10 uf capacitors in x5r/x7r technology have esr approximately 10 m . summary of design equations: ripples voltage/current, i nductor and capacitor: output ripple voltage, s l l l f c t i c ts t i t v 1 8 ) ( 1 8 ) ( ) ( 1 1 = = (3) inductor ripple current, ) ( 1 8 ) ( 1 t v f c t i l s l ? = (4) output inductor, ) ( ) ( ) ( 1 1 1 t i f vo vin d t i vo vin dts l l s l ? ? = ? (5) output capacitor, vo f i c s l 8 1 1 since vo c ts t i q l ? = ? ? = 1 2 2 ) ( 2 1 1 (6) output filter cut-off frequency, 1 1 2 1 c l f c = (7)
dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 5 overview of synchronous co nverter power loss: [1] the losses in the synchronous converter?s power switches ca n be defined by: bd gate sw c total p p p p p + + + = (8) where p c is the conduction loss, p sw is the switching power loss, p gate is the gate drive loss and p bd is the body diode loss. in addition, i nductor equivalent dc resistance losses and output capacitor?s esr loss play signi ficant role in the converter design. mosfet q1 and q2?s power loss: [1] the conduction losses: (replace d to 1-d for sync fet, q2): ) ( 2 ) ( on ds o c r d i p ? = (9) the gate-charge losses: s g gs c g f q v p ? ? = ? (10) the switching losses: figure 5: transitions waveform s of mosfet for inductive load the switching loss is, ) ( ) ( off t on t switching p p p + = 2 ] } { [ ) ( ) ( ) ( ) ( (max) s off t off ds on t on ds ds f t i t i v ? ? + ? = (11) mosfet body diode loss: [1] the body diode loss is a function of dead time and in every switching cycle; there are two dead-time intervals, td1 and td2. the dead-tim e is defined as the ti me required when both the mosfets q1 and q2 are off in order to prevent shoot-through.
dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 6 we can write as: 2 1 td td bd p p p + = (12) where ptd1 is the body diode loss during dead time td1 and ptd2 is the body diode loss during dead time td2. s rr rr in s l o f rr cd td f t i v f td i i v p p p ? ? ? ? + ? ? ? ? ? ? ? ? ? ? = + = 2 1 1 2 1 1 1 (13) () s l o f rr cd td f td i i v p p p ? ? ? ? ? ? ? ? + ? = = = 2 2 0 2 2 2 (14) pwm gate driver power loss: [1] the power dissipation in the driver is defined by, s dd onl g driver f v q p ? ? = ) ( (15) where q g(onl) is the total gate charge of the mosfet and v dd is the driver power supply. the gate ?point of voltage? is, fs o th sp g i v v + = (16) the driver current is, gate up pull driver sp dd h l driver r r v v i + ? = ? ? ) ( ) ( (17) gate down pull driver sp dd l h driver r r v v i + ? = ? ? ) ( ) ( (18) the rise time is, ) ( ) ( ) ( h l driver on g on t i q t ? = (19) the fall time is, ) ( ) ( ) ( l h driver on g off t i q t ? = (20) if an external schottky diode (d1) is used across q2, the schottky?s capacitance needs to be charged during q1 turn-on. the power lo ss to charge the schottky?s capacitance is, 2 2 ) ( s in schottky schottky c f v c p ? ? = (21)
dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 7 design example 1: assume design parameters as vin=12v, vo=3.3v and io=12a. table 1: design consideration 1 for synchronous buck converter input voltage, vin 12v output voltage, vo 3.3v output current, io 12a assume the output rippl e voltage is within v t v l 033 . 0 ) ( . when the output capacito r (c1) is 10uf , the inductor l1 values for the range of switching fre quencies from 100 khz to 500 khz are given in table: 2 based on equations 3-7. table 2: when c1= 10uf vin (v) vo (v) d v l (v) fs (khz) c1 (uf) ? l1 (a) l1 (uh) fc (khz) 12 3.3 0.275 0.033 100 10 0.264 90 5.31 12 3.3 0.275 0.033 200 10 0.528 45.31 7.48 12 3.3 0.275 0.033 300 10 0.792 30.20 9.16 12 3.3 0.275 0.033 400 10 1.056 22.65 10.60 12 3.3 0.275 0.033 500 10 1.32 18.12 11.83 synchronous driver controller: isl6594d from intersil: based on equation 18 and 19, from isl6594d dr iver datasheet, given high-side: tr=26ns, tf=18ns and source/sink current = 1.25/2a (m ax). for low-side, trr=18ns, tf=12ns and source/sink current = 2/3.0 a (max): table 4: from datasheet high-side rise time source current (a) required qg(on) source 26 ns 1.25 32.5nc sink 18 ns 2 36nc low-side rise time source current (a) required qg(on) source 18ns 2 36nc sink 12ns 3 36nc
dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 8 isl6594d specification: recommended devices for this application: 1. ixta90n055t2 vds = 55v, id25=90a qg(on) = 42nc, qgs = 14nc, qgd = 8.5nc, td(on) = 19ns, tr = 21ns, td(off) = 39ns, tf = 19ns. rds(on) = 8.4m vgs(th) = 2-4v, g fs = 43 ciss = 2670pf, coss = 420pf, crss = 100pf or, 1. ixta110n055t2 vds = 55v, id25=110a qg(on) = 57nc, qgs = 16nc, qgd = 11nc, td(on) = 18ns, tr = 25ns, td(off) = 40ns, tf = 23ns. rds(on) = 6.6m , vgs(th) = 2-4v, g fs = 49 ciss = 3060pf, coss = 497pf, crss = 105pf analysis based on above ixta90n055t2: nc nc nc q sw g 5 . 15 2 14 5 . 8 ) ( = + = the ?point of voltage? is defined by, fs o th sp g i v v + = v 35 . 3 43 15 3 = + = the driver current is, gate up pull driver sp dd h l driver r r v v i + ? = ? ? ) ( ) ( a 33 . 1 5 65 . 6 2 3 35 . 3 10 = = + ? =
dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 9 gate down pull driver sp dd l h driver r r v v i + ? = ? ? ) ( ) ( a 58 . 1 2 2 . 2 35 . 3 10 = + ? = the rise time is, ns ns ns t on t 36 10 26 ) ( = + = the fall time is, ns ns ns t off t 28 10 18 ) ( = + = high-side mosfet loss (q1=ixta90n055t2): the conduction loss is, d r i p on ds o q cond ? ? = ) ( 2 1 _ mw 332 332 . 0 275 . 0 0084 . 0 12 2 = = ? ? = the gate-charge losses: (assume fs = 200 khz) mw x x x x f q v p s g gs q gc 84 10 200 10 42 0 . 10 3 9 1 _ = = ? ? = ? and estimated switching loss is, pt 2 ] } { [ ) ( ) ( ) ( ) ( (max) s off t off ds on t on ds ds f t i t i v ? ? + ? = 3 9 10 200 10 ) 28 36 ( 2 12 12 x x x ? + ? ? = = 0.921w=921mw total high-side losses: 332m w+84mw+921mw = 1337mw=1.337w low-side mosfet loss (q2): the conduction loss is, ) 1 ( ) ( 2 2 _ d r i p on ds o q cond ? ? ? = mw w 877 877 . 0 725 . 0 0084 . 0 12 2 = = ? ? = the gate-charge loss: mw x x x x f q v p s g gs q gc 84 10 200 10 42 0 . 10 3 9 1 _ = = ? ? = ? total low-side losses: 877mw+84mw =961mw isl6594d driver loss: from datasheet: v dd = 5v table 6: ixs839 driver out put stage from datasheet driver pull up resistance r driver(pull_up) 3.0
dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 10 the power dissipation in the driver is defined by, sw dd total g thjc a j driver f v q r t t p ? ? = ? = ) ( where v dd = 10v and f s = 200 khz (assume for this case) the estimated driver power dissipation, mw p d 84 10 200 10 10 42 3 9 = ? ? ? ? ? dead-time power loss: [3] the dead-time is defined as the time required when both the mosfets are off in order to prevent shoot-through. in this period, th e schottky diode (or integral body diode is forward-biased and provided a power loss defined by, driver ixs839 provides delay time in the datasheet, ) / 5 . 0 ( ) ( ) ( _ pf ns pf c ns t delay time delay ? = (22) assume, ns t t d d 100 2 1 = = , which provides pf pf c delay 200 ) ( = s rr rr in s l o f rr cd td f t i v f td i i v p p p ? ? ? ? + ? ? ? ? ? ? ? ? ? ? = + = 2 1 1 2 1 1 1 3 9 3 9 10 200 10 37 2 . 2 12 2 1 10 200 10 100 2 528 . 0 12 85 . 0 x x x x ? ? ? ? + ? ? ? ? ? ? ? ? ? ? = ? ? = 0.19905+0.09768= 0.297w= 297mw () s l o f rr cd td f td i i v p p p ? ? ? ? ? ? ? ? + ? = = = 2 2 0 2 2 2 3 9 10 200 10 100 2 528 . 0 12 85 . 0 x x ? ? ? ? ? ? ? ? + ? = ? =0.208w= 208mw mw mw mw p p p td td bd 505 208 297 2 1 = + = + = synchronous converter efficiency: if we neglect inductor?s dc power loss and capacitor?s esr loss then the total estimated power loss, p loss = 1337mw+1007mw+84mw+505 mw=2933mw= 2.933w given output power, po = vo*io = 3.3*12= 39.6w estimated input power, pin= 39.6+2.933=42.6w the efficiency is defined as, pin po iin vin voio = ? = (23)
dc to dc synchronou s converter design abdus sattar, ixys corporation ixan0068 11 the estimated efficiency, % 93 93 . 0 6 . 42 6 . 39 = = = %, estimated input current: if we assume only 93% efficiency, then th e estimated input current can be obtained, estimated input current, ? = vin voio i in = a 5 . 3 93 . 0 12 12 3 . 3 = ? ? a bootstrap circuit design: [3] selecting bootstrap circuit com ponents are done with considerat ion of the electrical rating and characteristics of the high-side mosfet (q1). the capacitance is defined by datasheet of ixs839 driver, bst total g bst v q c = ) ( (24) where q g(total) is the total gate char ge of high-side mosfet (q 1 ), and vbst is the allowable voltage droop in q 1 . assume this voltage droop equal to 0.1v. uf mv nc c bst 210 . 0 200 42 = = the bootstrap diode and capacito r voltage rating should be dd in pacitor diodeandca bootstrap v v v + > _ the average forward current is defined by, sw total g avg f f q i ? = ) ( ) ( (25) ma 5 . 10 10 250 10 42 3 9 = ? ? ? = ? bibliography [1] ?synchronous buck mosfets loss calcu lation? an-6005, jon klein, fairchild semiconductor, 01/04/2006, www.fairchildsemi.com [2] ?examination of reverse recovery losse s in a synchronous buck converter circuit? application note from silicon se miconductor, 2003, www.siliconsemi.com [3] datasheet for isl6594d ?advanced sync hronous rectified buck mosfet driver? from intersil corporation, 2007, www.intersil.com

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